Semiconductor device and method of fabricating a semiconductor device

ABSTRACT

A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device. A method is also provided for the formation of shallow junctions in a semiconductor substrate by diffusion of dopant from an implanted layer contained within a dielectric layer into the semiconductor surface. Further, the ion implanted layer is provided with a second implanted species, such as hydrogen, in addition to the intended dopant species, wherein said species enhances the diffusivity of the dopant in the dielectric layer.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of and priority to U.S. ProvisionalApplication No. 60/392,023, and U.S. Provisional Application No.60/391,802, both filed on Jun. 26, 2002.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to semiconductor devices and in particular to theprocesses used to fabricate them.

2. Description of the Prior Art

The process for fabricating conventional CMOS (Complementary Metal OxideSemiconductor) semiconductor devices is well known and includes thesteps of creating a gate dielectric layer, depositing polysilicon gateelectrode material, patterning the polysilicon/dielectric gate stackinto the gate electrode, implanting a drain extension implant, creatingsidewall insulator structures (spacers), implanting a source/drainimplant, and providing a heat treatment to diffuse and electricallyactivate the implanted layers. The implants can be of n-type or p-typedopants, for the formation of N-channel or P-channel devicesrespectively.

There are various technical issues related to conventional CMOSprocesses as technology scaling progresses with regard to the doping ofthe gate electrode. First, as the gate dielectric thickness is scaleddown, the field intensity at the gate electrode/gate dielectricinterface increases with the result that the gate electrode experiencesdepletion of charge starting at the dielectric interface. This conditionis undesirable because it has the effect of increasing the effectivegate dielectric thickness, and modulating the threshold voltage.Further, there is a competing issue that attempts to increase the dopingof the gate electrode at the electrode/dielectric interface whichenhances the risk of dopant diffusion through the gate dielectric andinto the channel, particularly for boron doped gates. Dopant penetrationof the gate dielectric is undesirable because it changes the thresholdvoltage. The device is sensitive to dopant penetration of the gatedielectric because the doping concentration in the channel region underthe gate is low; therefore small amounts of dopant diffusing through thegate dielectric have significant effects.

There are two unit processes involved in the gate doping processes thatinteract to determine the extent of gate depletion and gate dielectricpenetration. The first is the ion implant which provides the dopantatoms, and the second is the heat treatment, or annealing, needed toactivate the implanted dopant, and which also diffuses the dopantthrough the gate material. The ion implant energy is chosen to be low,even though this compromises productivity, to ensure that no dopant isimplanted through the gate oxide, since the underlying channel region isdoped with a low concentration. This requires that the dopant bediffused through the gate layer to provide dopant at the gateelectrode/gate dielectric interface where it is needed to prevent gatedepletion. However, the gate material is usually polysilicon, which hasvery nonuniform diffusion characteristics. As such, there is very fastdiffusion down to the grain boundaries in the polysilicon, so somedopant reaches the gate electrode/gate dielectric interface quickly, yetmost of the dopant still needs to diffuse to fully dope the polysilicongrains and achieve high conductivity. The grain boundary dopant at thegate electrode/gate dielectric interface is then a risk for gatedielectric penetration as the heat treatment continues. This risk isincreased as the heat treatment goes to higher temperatures and longertimes. There are practical limits to the reduction of time/temperaturefor the gate electrode anneal, due to the need to diffuse the dopant tothe gate electrode/gate dielectric interface and the need toelectrically activate the implanted dopant, for example, as disclosed inM. Kase, et al. “FEOL Technologies for Fabricating High PerformanceLogic and System LSI of 100 nm node, 12th International Conference onIon Implantation Technology Proceedings, 1998, p. 91.

The technologies that have been proposed to address these issues includeoxynitride gate dielectric, SiGe gate electrode material, and metal gateelectrode materials. The oxynitride gate dielectric is useful for thereduction of the boron penetration through the gate oxide, but does nothelp with the gate depletion effect. The SiGe gate material also reducesboron diffusion and thus helps with gate penetration while increasingthe effective doping concentration, which also helps with the gatedepletion. The problem is that the SiGe gate material degrades the NMOScharacteristics and thus requires complex selective technologies toachieve a full CMOS solution. The metal gate approach solves the boronpenetration problem (no boron to diffuse) and the gate depletion issue(near infinite charge concentration) but makes setting the thresholdvoltage for NMOS and PMOS simultaneously very difficult. The metal gateapproach also has significant challenges in process integration; sincethe metal layers are not physically stable at the high temperatures ofthe heat treatments required for implant activation, such as required bythe source and drain regions.

The conventional device faces other limiting factors as technologyscales. With continued scaling, for example <0.1 um technology, theconventional device suffers from the need to provide sufficient gateoverlap of the drain extension region to ensure high performanceoperation. In particular, the extrinsic series resistance becomes alimiting factor as the overlap regions are scaled. A recent analysis, asreported by Ghani et al, Symposium VLSI Technology, pages 17-18, 2001,has shown that an asymmetric structure has the potential to allowfurther scaling while maintaining high performance devicecharacteristics. However, the process used by Ghani, et al in thedemonstration devices is very constraining relative to large-scaleproduction requirements: the structure requires a tilt implantselectively on the source side and not the drain side. To manufacturedevices with such a structure would require limiting the layout so thatall sources are to one side and all drains to the other, making thecircuit very large.

There is also a trend to form shallow semiconductor junctions. Therequirement for shallow junctions is a direct result of the continuedscaling of semiconductor technology wherein there is a constantprogression to smaller devices. As the devices are made smaller, thereare many features of the fabrication process that must be modified, or“scaled” in order to maintain proper functionality of the transistor andother circuit elements required. The impact on junction formationtechnology is that it is expected that the junction depth would scale astechnology scales, that is, the junctions become shallower as the gatelength becomes shorter. In this way, the transistor functionality ispreserved.

There are difficulties with continuing the historical methods of scalingthe junction depth. In particular, the conventional method of formationof such junctions is the use of ion implantation to introduce the dopantinto the semiconductor substrate, followed by a heat treatment step tomake the dopant atoms electrically active. To achieve shallowerjunctions, the ion implantation must be performed with lower energy, sothat the atoms do not penetrate into the semiconductor substrate as far.In general, shallow junctions require an ion implant energy of less than5 keV, while ultra-shallow junctions require ion implant energy of lessthan 1 keV (for boron implants). These implants have low productivity ona conventional implanter because they are in the regime where Child'sLaw applies; implants with energy of less than 10 keV. In this regime,the implanter's beam current is limited by space charge effects, with amaximum current that is proportional to the extraction voltage to the3/2 power. The conventional means of increasing the productivity in thisregime is to implement an acceleration/deceleration configuration forthe implanter: the beam is extracted at high energy to avoid the spacecharge limit imposed by Childs Law, and then decelerated before thewafers to implant with the correct energy. While this method is able toincrease productivity by around 2×, the deceleration beam has issueswith energetic contamination and nonuniformity of implant results.

There are further issues with the conventional implant process for theformation of ultrashallow junctions in that the implant creates defectstructures within the silicon implanted layer that pose more of an issueas the energy is reduced and the layer becomes shallower. First, thedensity of created defects increases quickly because the implantedvolume of the substrate material is reduced as the implant is madeshallow. Since the doses are either the same or increasing, thereduction of implant depth corresponds to an increase in both thedensity of implanted dopant and the implant defects. As the defectdensity increases, the probability of interaction increasesdramatically, with the problem that combinations of defects make morecomplex defect structures which are very difficult to anneal. It may benoted that the high density of implanted dopant, boron for example, alsoincreases the probability that dopant complex structures will form. Thisis particularly an issue when the dopant concentration exceeds the solidsolubility, since the supersaturated dopant tends to precipitate intoundesirable structures. For example, supersaturated boron tends toprecipitate into silicon boride (SiB4), a structure which binds theboron into electrically inactive position, rendering that component ofthe boron implant completely ineffective. As the energy is reduced, moreof the implanted dose resides in a region where the concentration isabove the solubility, so the effectiveness of the implant decreases withenergy.

The conventional process also places extreme constraints on the heattreatment, or anneal, used to make the implanted dopant electricallyactive. There is a strong conflict between the need to heat thesubstrate to high temperatures to effectively activate the implanteddopant versus the need to limit the temperature and time of the annealto prevent diffusion. This conflict has lead to the development of aprocess called the spike anneal, where the temperature is ramped quicklyto a peak temperature, and then immediately ramped down, such that theresidence time at the maximum temperature approaches zero. Such ananneal is necessary for the formation of ultrashallow boron junctions tominimize the diffusion of boron.

It has been proposed to address some of these issues with the formationof ultrashallow junctions by implanting into a surface oxide layer andthen diffusing through the oxide into the substrate to form thejunction, for example, as discussed in Schmitz, et al, “Ultra-ShallowJunction Formation by Outdiffusion from Implanted Oxide” IEEE-IEDM '98,p 1009; and Schmitz, et al, “Shallow Junction Fabrication by RapidThermal Outdiffusion from Implanted Oxides” Proceedings of Advances inRapid Thermal Processing, Electrochemical Society, Seattle Wash., 1999,p. 187. This approach has the advantage of reducing or eliminating thedefect formation in the semiconductor substrate by placing most of theimplant damage into the oxide layer. The method also relaxes theconstraints on annealing because most of the diffusion is now throughthe oxide layer. The method has the disadvantage, though, that diffusionthrough oxide is generally slower than through silicon, for example, asdiscussed in Fair, “Physical Models of Boron Diffusion in Ultrathin GateOxides” J. Electrochem. Soc, 144, 1997, p. 708-717.

A further issue with the conventional process is the difficulty inavoiding implanting into an oxide while attempting to form anultrashallow junction, for example, as discussed in Krull, et al, “Theimportance of the native oxide for sub-keV ion implants,” Proc. 12thInternational Conference on Ion Implant Technology-1998, p 1113, 1999.As technology scales and the implant energy is reduced, it becomesincreasingly difficult to remove the surface oxide well enough that itdoes not interfere with the ion implant process. As discussed by Krull,et al, even a native oxide (oxide that forms on a silicon wafer just byexposure to air at room temperature) is thick enough that a boronimplant with energy of 250 eV places most of the atoms into the oxide(1.5 mm) rather than into the silicon as intended. Since the nativeoxide forms at room temperature in air, extreme measures are required toimplant into truly bare substrates, such as an in-situ oxide stripinside the vacuum system of the ion implanter. There are no productionimplanters with such capability. Absent the ability to implant intotruly bare substrates, the production solution must involve controllingthe thickness of oxide present and implanting into that oxide. Such aprocess will be required to provide production level repeatability.

SUMMARY OF THE INVENTION

The present invention uses a two-deposition gate formation process toallow alternative process conditions, which address the issues of gatedepletion and dopant penetration of the gate dielectric observed inconventional technologies. In particular, the present invention relatesto the formation of a gate electrode by a combination oftwo-deposition-plus-implant sequences. The first deposition is thin andits corresponding implant is very shallow, to directly place a maximallyeffective dose as close to the gate electrode/gate dielectric interfaceas possible. The emergence of cluster ion implants which enable highdose, ultra low effective-energy implant processes, eliminates theprevious constraints on doping very thin layers. The second depositioncompletes the gate electrode to a conventional thickness and allows theindependent selection of the ion implant and heat treatments for thesecond deposition.

It may be noted that the advent of spike annealing further enables theformation of very shallow, highly activated dopant layers. A spikeanneal is a rapid thermal process or heat treatment in which the time atthe highest temperature approaches zero: the temperature is ramped upvery quickly and immediately ramped down as quickly as possible. In thepresent invention, the formation of the shallow doped layer at the gateelectrode/gate dielectric interface eliminates one of the constraints onthe implant and heat treatment normally used for single gate processes:since there is no longer a need to diffuse the dopant through the gateelectrode layer to the gate dielectric interface to combat gatedepletion, a spike anneal can be used, further reducing the risk ofdopant penetration of the gate dielectric.

Further benefits of this two-deposition gate formation process can berealized when two gate-patterning steps are included. In particular, onebenefit of utilizing two patterning steps is that the drain extensionimplant can be used for both the first level gate doping step and thedrain extension implant, eliminating one shallow implant from theprocess. Next, the use of two patterning steps allows the freedom tochoose to offset the second pattern towards the source side of the gate.This would create an asymmetric source/drain transistor with much largeroverlap of the drain extension region on the source side than the drainside. This is an effective means of creating the kind of transistorbehavior described by Ghani, et al, while avoiding other layout andprocess constraints.

Another aspect of the invention relates to a method of fabricating anultrashallow semiconductor junction by ion implantation of a dopantspecies into a dielectric layer on the surface of a semiconductorsubstrate and diffusing the dopant through the dielectric layer and intothe semiconductor substrate, thereby creating a shallow semiconductorjunction. The method is further comprised of implanting an additionalspecies, or more than one additional species, where the action of theadditional species is to enhance the diffusion of the dopant through thedielectric layer, thereby making the process more effective. One exampleof such a process is the implantation of a boron/hydrogen cluster ioninto a silicon dioxide layer atop a silicon wafer. In this case, thehydrogen is known as set forth in the Fair reference, supra, to enhancethe diffusion of boron in silicon dioxide, allowing management of theannealing process used to enable diffusion. This enhancement of thediffusion rate in oxide allows the relaxation of other processconstraints, particularly on the time and temperature of the annealingtreatment.

DESCRIPTION OF THE DRAWINGS

These and other advantages of the present invention will be readilyunderstood with reference to the following specification and attacheddrawings wherein:

FIGS. 1 a-1 d are process flow diagrams showing a two-deposition gateformation process in accordance with the present invention.

FIGS. 2 a-2 c are process flow diagrams showing the two-deposition gateformation process achieving self-aligned drain extension and source anddrain regions in accordance with the present invention.

FIGS. 3 a-3 e are process flow diagrams showing the two-deposition gateformation process with two gate patterning steps to form an asymmetricoverlap transistor structure in accordance with the present invention.

FIGS. 4 a-4 e are process flow diagrams showing the process sequence forformation of the notched transistor structure in accordance with thepresent invention.

FIG. 5 is a graphical illustration of boron concentration as a functionof the gate electrode depth for the two step gate formation process inaccordance with the present invention.

FIG. 6 is a diagram of semiconductor substrate with surface dielectriclayer.

FIG. 7 is a diagram showing ion beam forming an ion implanted layerwithin dielectric layer in accordance with another aspect of the presentinvention.

FIG. 8 is a diagram showing substrate after heat treatment, where dopanthas diffused out of dielectric layer and formed a shallow junction inaccordance with the embodiment of the invention illustrated in FIG. 7.

DETAILED DESCRIPTION

The present invention relates to a method for forming the gate electrodeof an MOS transistor with a two-deposition process, as a means ofaddressing the issues of gate depletion and boron penetration of thegate dielectric, without requiring new materials. The present inventionalso relates to a method for forming an ultrashallow junction in asemiconductor substance.

Formation of Gate Electrode

As mentioned above, one aspect of the invention relates to the formationof a gate electrode of a MOS transistor by way of a two step depositionprocess. In the two-deposition process, the first step is the depositionof a thin layer of electrode material, followed by a shallow ionimplantation to provide a high concentration of dopant near the gateelectrode/gate dielectric interface. The second step is also a gatelayer deposition, followed by ion implantation, such that the totalthickness of the two layers is comparable to a conventional single layergate electrode structure.

In the following description of embodiments of the invention, certainspecific details are discussed. It should be understood these detailsare examples only. Specifically, the examples are intended to illustratea PMOS (P-channel Metal Oxide Semiconductor) transistor of the 0.13 umtechnology node. However, the principles of the present invention areclearly applicable to other applications, including application to NMOStransistors.

One embodiment of the invention relating to the formation of a gateelectrode is shown in FIGS. 1 a-1 d. In particular, FIG. 1 a shows asemiconductor substrate (10) that has been processed by conventionalCMOS processing steps through the steps of well formation (11), trenchisolation (12) and a gate dielectric formation (13). The well structureis, for example, a doped n-type for the PMOS transistor. The gatedielectric thickness is around 2 nm for the 0.13 um technology node. Thefirst gate deposition (14) with a thickness of 15-20 nanometer (nm), forexample, is formed directly on top of the gate dielectric layer (13).Typically this deposition (14) is either a layer of amorphous silicon orpolycrystalline silicon (polysilicon). The interface (9) between thegate dielectric and the first electrode layer (14) of the gate electrodeis where gate depletion occurs in the conventional device.

FIG. 1 b shows the next step of the process, which is the shallow ionimplant to dope the first gate electrode layer. The requirements forthis implant are around 500 eV boron to a dose of around 1×10¹⁵ cm⁻². Analternative process is a decaborane implant at 5.5 keV to a dose of1×10¹⁴ cm⁻², or other process-equivalent implant step. It may be notedthat the energy of the implant must be low so that the dopantpenetration is shallow; in particular, none of the implanted dose(<0.1%) should go through the deposited layer and gate dielectric, sincethe channel region must be doped with a low concentration to set thethreshold voltage correctly. It may be noted that this constraint issevere for a conventional implant process because the productivity ischallenged by the low energy required and the energy contamination thatresults from deceleration of the ion beam is a risk for penetrationthrough the gate stack and into the channel.

The processing continues as shown in FIG. 1 c, which illustrates thesecond deposition layer (17) directly deposited over the firstdeposition layer (14). Since together the first and second depositionlayers 14 and 17 respectively, form the gate electrode, no interveninglayers are required. The second deposition layer (17) may be eitheramorphous silicon or polysilicon. It is noted that an amorphous silicondeposition offers some advantages in terms of layer smoothness andchanneling avoidance but the amorphous silicon does convert topolysilicon later in the process flow, during a heat treatment. Thethickness of the second deposition layer (17) may be around 130 nm, forexample, so that the total of first and second deposition is around 150nm, a full thickness gate electrode.

FIG. 1 d illustrates a second ion implantation or doping step, forexample, an ion implant of boron, boron molecules or boron clusters withthe boron equivalent energy of around 2 keV and a high dose of around5×10¹⁵ cm⁻². From this point, the conventional CMOS process continueswith gate patterning, spacer formation, source and drain formation, etc.

One embodiment of the present invention includes the step of patterningthe gate stack (18) (gate oxide/first electrode layer/second electrodelayer) prior to the second implantation. One advantage of thisembodiment is self-alignment between the drain extension andsource/drain regions and the patterned gate stack (18). This processsequence is shown in FIGS. 2 a-2 c. In particular, FIG. 2 a shows thesubstrate from the previous process sequence after the processing asillustrated in FIG. 1 c and patterning of the gate stack 18, forexample, by conventional photolithography. For a 0.13 um technologynode, the gate length is in the range of 60-120 nm. FIG. 2 b shows theprocess continuing through the step of drain extension implant. First, aphotoresist (PR) layer (23) is applied and patterned such that PMOSareas are exposed (i.e. drain extension regions 38 and 39). For thedrain extension implant, the ion beam (21) is a boron implant of energyaround 500 eV and dose around 5×10¹⁴ cm⁻². A boron cluster implant ormolecular implant, for example, decaborane, as disclosed in commonlyowned U.S. Pat. No. 6,452,338 with process equivalent conditions couldbe used. The penetration of this implant into the exposed substrateareas forms the drain extension region (22) as shown in FIG. 2 c and mayalso form an implanted layer at the surface of the gate electrode (thegate electrode surface may be protected, if the implanted region is notdesired). As shown in FIG. 2 b, the inside edge of the drain extension22 is aligned with the gate stack edge, thus resulting inself-alignment. The PR layer (23) is removed by conventional techniques,and insulator spacers (25) are formed on the sidewalls of the gate stack(18) by way of another photoresist layer (28) that is applied andpatterned so that the PMOS device areas are exposed to define drain andsource regions 30 and 31, respectively. The second ion implantation stepis now performed to create a deep source (26) and drain (27) layers andsimultaneously provide the dopant for the full gate electrode (29). Theprocess conditions for the second implant are an energy of around 2 keVand dose of 5×10¹⁵ cm⁻² for boron, with process-equivalent conditionsfor boron cluster ion implants. The second photoresist layer (28) isthen removed and conventional CMOS processing is continued if desiredincluding interlevel dielectric deposition, contact formation,metallization, etc.

An additional aspect of the present invention includes the introductionof an additional gate-patterning step after the first set ofdeposition/implant processes. In this embodiment of the invention, thereare two gate-patterning steps required, since the second electrodedeposition layer will also need to be patterned into the gate electrode.It is expected that a two gate-patterning approach is only used when anasymmetric transistor structure is desired because of the difficulty inoverlaying the two gate patterns. With two gate-patterning steps, theasymmetry can be designed into the two gate patterns, providing controlover the asymmetric properties. Two asymmetric structures will bediscussed: the asymmetric overlap structure and the notched gatestructure.

More particularly, an asymmetric overlap transistor can be formed viathe two gate-patterning process sequence. One aspect of this embodimentof the invention is that the electrode implant step can be used to formthe drain extension layer, since the implant requirements are thesimilar. An additional aspect of this embodiment is the ability to formthe asymmetric overlap transistor structure by offsetting the two gatepatterns. This process sequence is shown in FIGS. 3 a-3 e. In FIG. 3 a,the substrate from FIG. 1 a has been processed through a gate-patterningstep. For the 0.13 um technology node, the gate length for this patternis around 50-80 nm. At this point, a photoresist layer (42) is appliedand patterned, as shown in FIG. 3 b, to expose drain extension regions38 and 39 of the dielectric layer 13. A shallow ion implant step isprovided, such that the drain extension (43) is created in the exposedsource and drain regions and the exposed surface of the first gateelectrode becomes doped (44). The implant conditions for this implantmay be a decaborane implant of 5.5 keV to a dose of 0.5-1×10¹⁴ cm⁻², orprocess equivalent implant by boron or boron cluster, such asdecaborane. At this point, the photoresist layer (42) is removed byconventional techniques, and the second gate deposition (45) isprovided, creating the structure shown in FIG. 3 c. Next, the gateelectrode layer is patterned, with the pattern being larger and havingan offset to the first gate pattern layer. The resulting gate electrodestack is shown in FIG. 3 d. The overlap of the second gate layer beyondthe first gate layer may be constrained to the source side of thetransistor as shown (46). In this way, very small transistors can beformed without degradation of the drain saturation current, IDSAT, asdiscussed by Ghani, et al., supra. The process continues, as shown inFIG. 3 e, with the formation of gate sidewall spacers (51) and theapplication and patterning of a photoresist layer (50) to expose onlythe PMOS transistors and thereby define drain and source regions 38 and39 of said dielectric layer 13. Then, the second ion implant isperformed with ion beam (47) conditions of 2 keV, 5×10¹⁵ cm⁻² boron, ora process-equivalent cluster ion implant. FIG. 3 e shows the formationof the source and drain regions (48) and the second ion implant layer inthe gate electrode, by the penetration of this ion implant. At thispoint, the asymmetric overlap transistor structure is formed and thesubstrate would continue through a conventional CMOS fabricationsequence, through interlevel dielectric deposition, contact formation,metallization, etc. It may be noted that other variations of theasymmetric overlap transistor can be formed by variation of this method.

Another aspect of the present invention relates to the formation of anotched gate transistor structure by application of this method, such asshown in FIGS. 4 a-4 e. This process sequence starts with a substrateprocess through the first gate deposition and first gate implant, asillustrated in FIG. 1 b. At this point, the first gate electrode layeris patterned. The next step in the process is to provide the second gatedielectric (52) at the exposed semiconductor surface outside of thepatterned gate stack. The second gate dielectric is different from thefirst gate dielectric, and it's processing might include any of avariety of gate dielectric processing steps including: implantation of aspecies such as nitrogen into the existing gate dielectric, chemicaltreatment of the existing dielectric, such as exposure to ammonia athigh temperatures, clearing the existing dielectric and regrowth of adifferent gate dielectric, such as a different thickness of silicondioxide or an oxynitride dielectric with a different nitrogen content,deposition of an additional layer of gate dielectric, such as siliconnitride or hafnium or zirconium oxide or silicate, or a combination ofsuch processing. The second gate dielectric processing step provides adifferent gate dielectric than the first gate dielectric, so that thethreshold voltage of the second gate region is different than the first.Another option at this point is the application of a second thresholdadjust implant, as shown by ion beam (64) and the threshold adjustimplant layer (65). This ion implant may be a very light dose of range1×10¹³ cm⁻² of either conductivity type. In combination with the secondgate dielectric, this implant would set the threshold voltage of thesecond gate region.

As illustrated in FIG. 4 b, processing continues through the step ofsecond gate electrode deposition, which is deposited to a thickness suchthat the total thickness is conventional. This deposition may beamorphous silicon or polysilicon. The next step, as shown in FIG. 4 c,is the patterning of the second gate electrode deposition (54). Thefinal transistor structure thus includes two regions, which havedifferent gate dielectrics.

Next, a photoresist layer (55) is applied and patterned to expose thePMOS devices (i.e. drain extension regions 64 and 65) as shown in FIG. 4d. The drain extension (57) is then formed, by the implantation of aboron-containing ion beam (56). Typical conditions for this implant arean energy of 500 eV and a dose of 5×10¹⁴ cm⁻², or boron cluster implantwith process equivalent parameters. This implant also achievesself-alignment of the drain extension to the gate stack edge, in theconventional way. This implant will form a shallow doped layer (58) onthe surface of the gate electrode, unless coverage is provided. At thispoint, the photoresist layer (55) is stripped, and insulating sidewallspacers (59) are formed on the sidewalls of the gate electrode, as shownin FIG. 4 e. A new photoresist layer (62) is applied and patterned,again protecting NMOS regions and exposing PMOS regions (i.e. exposingsource and drain regions 66 and 67, respectively). Next, ion beam (60)is implanted to form the source and drain regions (61). The implant alsoprovides the gate electrode doping (63). At this point, the notched-gatetransistor structure has been formed and the substrate would continuethrough a conventional CMOS fabrication sequence, through interleveldielectric deposition, contact formation, metallization, etc. It may benoted that other variations of the notched-gate transistor can be formedby variation of this method.

One aspect of the present invention is to make certain that thecombination of first deposition thickness, first implantation depth(implant energy) and heat treatment are such that no boron penetrationof the gate oxide occurs. This requires that the first deposition bevery thin and that the first implant be very shallow, and the heattreatment is chosen to minimize diffusion. In one embodiment of thepresent invention, cluster ion implantation may be used for the firstimplantation step to a first deposition thickness around 20 nm and aspike anneal for the heat treatment. This combination of process stepswill provide the structure necessary to minimize gate depletion andboron penetration of the gate oxide. Typical conditions include: firstdeposition thickness 20 nm, first implant of decaborane at approximately5 keV to a dose of 1×10¹⁴ cm⁻², and a spike anneal to a temperature of100° C. These conditions should ensure that no boron penetration of thegate dielectric occurs.

FIG. 5 demonstrates that appropriate implant conditions can be achieved.The simulations were performed using, for example, SRIM 2000, a programthat calculates the depth and distribution of ions implanted intomaterials, as set forth in J. Ziegler et al., “The Stopping and Range ofIons in Solids; Pergamon Press, New York 1985. In this example, thenominal implant parameters are modeled to determine the depth profilesthat result from the two implant processes. The first deposition (71) ismodeled as a polysilicon deposition that is 15 nm thick. The firstimplant conditions are modeled as a 500 eV boron implant of 1×10¹⁵ cm⁻²dose, with resulting profile (72) As seen in FIG. 6, none (<0.1%) of theimplant reaches the gate oxide interface (75) and certainly none getthrough the gate dielectric into the underlying silicon. The seconddeposition (73) is modeled as a 125 nm deposition of polysilicon,followed by a boron implant with energy 2 keV and dose 5×10¹⁵ cm⁻² withresulting profile (74). It is noted that the second implant profile (74)is fully contained with the gate electrode layer. For the NMOS device,arsenic ion implant would be used, and since arsenic is a higher massatom, it's penetration depth is less and therefore no risk of gatepenetration would exist.

Formation of Ultrashallow Junction

Another aspect of the present invention relates to the formation of anultrashallow junction in a semiconductor substrate by implanting thedesired dopant into a dielectric layer on the surface of thesemiconductor substrate and diffusing the dopant out of the dielectriclayer and into the semiconductor substrate to form a junction. A secondspecies may be implanted into the dielectric layer, either at the sametime as the dopant or subsequently, to alter the diffusion properties ofthe dielectric/dopant system. An example of such a method is theimplantation of a boron hydride cluster into a silicon dioxide layer ona silicon wafer, wherein the hydrogen enhances the diffusion of boronthrough the oxide layer and thereby makes the formation of the boronultrashallow junction more effective.

The process starts with a semiconductor substrate 1, as shown in FIG. 6.Typically, the semiconductor substrate is a silicon wafer, but it couldbe a III-V semiconductor substrate also. Further, the semiconductorsubstrate would typically have doping to some level, it will be assumedthat the semiconductor substrate is doped n-type. On the surface of thissemiconductor substrate, there is a thin dielectric layer, 2. Thisdielectric layer would typically be silicon dioxide or silicon nitride,but other materials are possible. The thickness of the dielectric layeris subject to optimization, but would likely be in the range of 5-20 nmin thickness. The dielectric layer is in contact with the semiconductorsubstrate (1) at the interface (3) between the two materials.

As shown in FIG. 7, an ion beam (4) is directed at the surface, withsufficiently low energy that the ion implanted layer (5) is entirelycontained within the dielectric layer. Ion beam (4) can represent eithera single implant, such as a boron cluster ion, or a sequence ofimplants, such as a boron implant followed by a hydrogen implant. It maybe desirable that the dopant species implanted layer be completelycontained within the dielectric layer, as shown by implanted layer 5.For example, if the dielectric layer is silicon dioxide, and it is 20 nmin thickness, then a boron implant of 500 eV energy or less would becompletely contained within the dielectric layer. It is desirable tohave the second implant species entirely contained within the dielectriclayer also, to increase it's effectiveness, but there is no impact onthe resulting junction is a fraction of the second species enters thesemiconductor substrate. Next, a heat treatment is applied, wherein thetemperature and time have been optimized to provide enough diffusion forthe dopant species to diffuse out of the dielectric layer 2, through theinterface 3, and form a shallow junction 6 in the semiconductorsubstrate (1), as shown in FIG. 8.

This method has several features that make it attractive for implantingdirectly into a semiconductor substrate. First, the implantation processnecessarily introduces crystal defects into the semiconductor substrate,which are detrimental to achieving good electrical properties of thejunctions being fabricated. Containing the implant damage to thedielectric layer is beneficial both to the semiconductor devices beingfabricated and to the junction formation process itself. This is becausethe implantation defects do not cause degradation of the dielectriclayer since it is noncrystalline, and the defects will enhance thediffusion of the dopant through the dielectric layer.

The method discussed above relaxes the constraints on the heat treatmentprocess used to make the implanted dopant electrically active. The goalof the heat treatment is to place the dopant into substitutional siteswithin the semiconductor lattice, allowing the dopant to bond with thesemiconductor atoms and thereby gain its electrical activity within thesemiconductor system. In a conventional process, the implanted dopantoccupies mostly interstitial sites and a high temperature annealing stepis required to place the dopant into substitutional, electrically activesites. This high temperature process allows for substantial diffusion ofthe implanted dopant, however, which acts against the formation ofultrashallow junctions. In the conventional process, the optimization isreached with a spike anneal, wherein the temperature of the annealingstep is ramped to the highest temperature and immediately ramped backdown, in order to achieve electrical activity with the minimumdiffusion. With the proposed process, all of the dopant in thesemiconductor reached its position by diffusing, which means that it issubstitutional since the diffusing process is substitutional. Thus, adifferent optimization of the annealing step is required, since theanneal is now chosen to diffuse the dopant through the dielectric layerand just into the semiconductor substrate. It is expected that this isbetter accomplished with a lower temperature process with finite time,rather than the spike anneal.

The process in accordance with the present invention is more effectivethan that discussed by the Schmitz reference, supra, and includes theintroduction of a second species, for example, hydrogen. The diffusionof boron in silicon dioxide is slower than the diffusion of boron insilicon, presenting a limitation to the efficiency of the formation ofhigh concentration junctions. One way to manage this limitation is theenhancement of the diffusion rate in the dielectric by the introductionof hydrogen. It is shown by Fair that the presence of hydrogen canenhance the diffusion rate by a factor of two. The implantation of thehydrogen is an attractive process relative to the alternatives, whichwould normally be the introduction of hydrogen from the ambient duringdiffusion. Since the annealing process is high temperature (>800 C.),hydrogen is a dangerous gas to use as the annealing ambient, since it isflammable in contact with air. The normal means of performing a hydrogendiffusion in semiconductor technology is the use of an ambient composedof a mixture of hydrogen and nitrogen, since the mixture is much safer.However, the nitrogen effect is to retard the diffusion of boron insilicon dioxide, so the safe mixture does not provide much benefit.Implantation of the hydrogen is a very safe and effective way to enhancethe diffusion of boron in silicon dioxide.

A further aspect of the invention is the relaxation of many of theimplant constraints in the normal process. These constraints include theimplant dose and the implant energy. One aspect of this method is theenhanced utility of higher dose implants. In a conventional processwhere the implant is directly into the semiconductor substrate, there isa limit to the amount of dopant that can be implanted effectively, dueto the formation of alternative phases of various materials that renderthe dopant ineffective. For example, for the case of boron implant intosilicon, when the implanted concentration exceeds the solid solubilityof boron at the annealing temperature, the excess boron precipitates asa silicon boride phase, which renders the boron electrically inactiveand very difficult to recover. This mechanism places an upper limit onthe amount of electrically active boron that can be achieved by theconventional process. In the proposed method, the implanted dopant goesinto an amorphous dielectric layer, where no alternative phase materialshave been observed. Thus, all of the implanted boron contributes to theprocess of formation of the ultrashallow junction, through theestablishment of a diffusion profile through the dielectric layer. It isvery beneficial to this process that the diffusion profile containsconcentrations exceeding the solid solubility of boron in thesemiconductor, for example, since that can increase the flow of dopantsdiffusing to the semiconductor surface. Another aspect of the proposedmethod is that implanting into a surface dielectric layer can allow theimplant energy to be increased. The conventional method carries therequirement of extremely low implant energy because the implant depth isa critical factor in establishing the ultrashallow junction. In theproposed process, the implant energy is related to the dielectric layerthickness, which can be chosen to optimize the process. It is desirableto keep the oxide layer thin and utilize a low energy implant, but thispreference is to make the diffusion more effective rather than directlyimpacting the junction depth. Since the implant productivity is directlyrelated to implant energy, the proposed method is preferred.

Another aspect of the proposed method is the use of implanting thesecond species as a means of avoidance of some detrimental effects ofthis species. In particular, using the example of boron diffusionenhancement by hydrogen, it is detrimental to enhance the diffusion ofboron through the gate oxide layer, which occurs when anneals areperformed in a hydrogen ambient, or excess hydrogen is available duringany high temperature treatment. In the proposed method, the implantationof hydrogen places it exactly in the region where boron diffusion isdesired and it is masked out of other regions of the circuit. A furtheraspect of this method is that only sufficient hydrogen is introduced,since any excess hydrogen would be available to diffuse to other regionsand detrimentally enhance diffusion where it is undesirable. Since theenhancement effect is believed to be attachment of the hydrogen to thediffusing boron and diffusing as a cluster, a ration of 1/1 is the idealamount of hydrogen to introduce into the process. With implantation,this hydrogen is placed exactly in the volume wherein the boron ispresent and diffusing. The conventional methods, such as annealing in ahydrogen ambient, introduce copious amounts of hydrogen into all regionsof the semiconductor substrate, allowing for enhanced diffusion isregions where it is undesirable. A further embodiment of the proposedmethod would be to implant the two species separately, enabling theoption of masking the second species differently than the first species,such that only certain regions implanted with the first species receivethe diffusion enhancement. In this way, two different optimizations ofthe Source/Drain Extension could be achieved with only masking of thesecond implant. This would be useful in a process whereby varioustransistors with different properties are being fabricated with a singleprocess flow, which is typical in modern semiconductor fabricationprocesses.

For this aspect of the invention, it is highly undesirable that thedopant implant be performed on a decel type implanter. This is due tothe presence of energy contamination in the beam of every decelimplanter, to some degree. For commercially available systems, thisenergy contamination is in the range of 0.1-1.0% for production viableprocesses. In the conventional shallow junction process, thiscontamination, which is a fraction of the beam at higher energy,penetrates more deeply into the semiconductor substrate and forms a tailon the implanted profile, which can generally be managed in the processoptimization. In the proposed process this contamination is moredetrimental, since the higher energy beam will penetrate through thesurface dielectric layer and into the semiconductor substrate, formingan implanted region which is not desired. Since it is likely that theproposed process would utilize a higher dose than the conventionalprocess, the contamination concentration in the semiconductor would beproportionally higher than in the conventional case, exacerbating theproblem. Thus the preferred embodiment of this method would be a clusterimplant in drift mode, whereby both species of interest are implanted atthe same time without the presence of higher energy contamination.

The present invention has been described, along with severalembodiments. The present invention is not limited thereto. For example,it will be apparent to those skilled in the art that variousmodifications, alterations, improvements and combination thereof arepossible.

Obviously, many modifications and variations of the present inventionare possible in light of the above teachings. Thus, it is to beunderstood that, within the scope of the appended claims, the inventionmay be practiced otherwise than as specifically described above.

What is claimed and desired to be covered by a Letters Patent is asfollows:

1. A method for forming a gate electrode for a metal oxide semiconductordevice having a substrate and formed with a well and opposing trenchisolation portions with a first dielectric layer formed thereon, themethod comprising the steps of: (a) depositing a first gate electrodelayer on said first dielectric layer; (b) doping said first gateelectrode layer, defining a doped first gate electrode layer; (c)depositing a second gate electrode layer on said doped first gateelectrode layer; (d) doping said second gate electrode layer; and (e)heat treating the structure to activate the dopant materials.
 2. Themethod as recited in claim 1, wherein the said first gate electrodelayer and said second gate electrode layer together form a fullthickness gate electrode.
 3. The method as recited in claim 1, whereinthe step of depositing a first gate electrode layer comprises depositingamorphous silicon.
 4. The method as recited in claim 1, wherein the stepof depositing a first gate electrode layer comprises depositingpolysilicon.
 5. The method as recited in claim 1, wherein the step ofdepositing a second gate electrode layer comprises depositing amorphoussilicon.
 6. The method as recited in claim 1, wherein the step ofdepositing a second gate electrode layer comprises depositingpolysilicon.
 7. The method as recited in claim 1, wherein said step ofdoping said first gate electrode layer comprises doping said first gateelectrode layer with boron.
 8. The method as recited in claim 1, whereinsaid step of doping said first gate electrode comprises doping saidfirst gate electrode layer with decaborane.
 9. The method as recited inclaim 1, wherein said step of doping said second gate electrode layercomprises doping said second gate electrode layer with boron.
 10. Themethod as recited in claim 1, wherein said step of doping said secondgate electrode comprises doping said second gate electrode layer withdecaborane.
 11. A method for forming a metal oxide semiconductor (MOS)device having a substrate, comprising the steps of: (a) forming a welland opposing trench isolation portions in said first substrate; (b)depositing a first dielectric layer thereon; (c) depositing a first gateelectrode layer on said first dielectric layer; (d) doping said firstgate electrode layer, defining a doped first gate electrode layer; (e)depositing a second gate electrode layer on said doped first gateelectrode layer; (f) forming a gate stack from the combination of saiddoped first gate electrode layer and said second gate electrode layer,resulting in exposed portions of said first dielectric layer; (g)patterning a first photoresist to expose drain extension regions on saidfirst dielectric layer adjacent to said trench isolation portions; (h)doping said exposed portions of said gate stack and said firstdielectric layer forming drain extensions in said well between saidtrench isolation portions and said gate stack. (i) removing said firstphotoresist and patterning a second photoresist to form spacers adjacentopposing sides of said gate stack and exposing portions of said firstdielectric layer defining drain and source regions; (j) doping saidexposed portions of said first dielectric layer to form source and drainlayers within said well; (k) removing said second photoresist layer; and(l) providing heat treatment to diffuse the implanted dopant to causesaid implanted dopant to diffuse out of said first dielectric layer intosaid well.
 12. The method as recited in claim 11, wherein said step ofdoping said first gate electrode layer comprises doping said first gateelectrode layer with boron.
 13. The method as recited in claim 11,wherein said step of doping said first gate electrode layer comprisesdoping said first gate electrode layer with a boron cluster implant. 14.The method as recited in claim 11, wherein said step of doping saidfirst gate electrode layer comprises doping said first gate electrodelayer with a molecular implant.
 15. The method as recited in claim 11,wherein the step of doping said drain and source regions comprisesdoping said drain and source regions with boron.
 16. The method asrecited in claim 11, wherein the step of doping said drain and sourceregions comprises doping said drain and source regions with a boroncluster.
 17. A method for forming a metal oxide semiconductor devicehaving a substrate, comprising the steps of: (a) forming a well andopposing trench isolations in said substrate; (b) depositing a firstdielectric layer thereon; (c) depositing a first gate electrode layer onsaid first dielectric layer; (d) forming said first gate electrode layerinto a gate stack leaving exposed portions of said first dielectriclayer; (e) patterning a first photoresist layer to expose drainextension regions of said first dielectric layer; (f) doping said drainextension regions forming drain extension layers and said well; (g)removing said first photoresist layer; (h) depositing a second gateelectrode layer; (i) forming said second gate electrode stack to beoffset and larger than said gate stack formed from said first gateelectrode layer; (j) patterning a second photoresist layer to formspacers adjacent said second gate electrode stack to define drain andsource regions; (k) doping said drain and source regions to form drainand source layers in said well; and (l) removing said second photoresistlayer; and (m) providing heat treatment to cause said implanted dopontsto activate material implanted by said doping step.
 18. The method asrecited in claim 17, wherein said step of doping said drain extensionregions comprises doping said drain extension regions with decaborane.19. A method for forming a metal oxide semiconductor (MOS) device havinga substrate, the method comprising the steps of: (a) forming a well andopposing trench isolations in said substrate; (b) depositing a firstdielectric layer thereon; (c) depositing a first gate electrode layer onsaid first dielectric layer; (d) forming said first gate electrode layerinto an initial gate stack leaving exposed portions of said firstdielectric layer; (e) doping said gate stack and said exposed surfacesof said first dielectric layer; (f) depositing a second gate dielectriclayer, different than said first dielectric layer on said exposedsurfaces of said first dielectric layer; (g) depositing a second gateelectrode deposition layer on top of said initial gate stack and saidsecond dielectric layer; (h) forming the second gate electrodedeposition into a final gate stack; (i) patterning a first photoresistto expose said final gate stack and drain extension regions; (j) dopingsaid final gate stack and said drain extension regions; (k) removingsaid first photoresist; (l) patterning a second photoresist to form sidewall spacers adjacent to said final gate stack and to expose said drainand source regions; (m) doping said drain and source regions and saidfinal gate electrode stack to form drain and source layers in said well;(n) removing said second photoresist layer; and (o) providing heattreatment to activate material implanted by said doping step.
 20. Theprocess as recited in claim 19, wherein step (f) comprises implanting aspecies into said first dielectric layer.
 21. The process as recited inclaim 19, wherein step (b) comprises chemical treatment of the firstdielectric layer.
 22. The process as recited in claim 19, wherein step(b) comprises removal of said first dielectric layer and regrowth of asecond dielectric material different from said first dielectricmaterial.
 23. The process as recited in claim 1, wherein said first andsecond gate electrode layers together total a thickness of aconventional gate electrode layer.
 24. A process for forming anultrashallow junction in a semiconductor substrate as an integral partof a semiconductor device, the process comprising the steps of: (a)depositing a dielectric layer on said substrate; (b) doping saiddielectric layer; and (c) providing heat treatment to cause implantedions from said heat treatment to diffuse into said substrate forming ashallow junction.
 25. The process as recited in claim 24, wherein step(b) comprises doping said dielectric layer with a single ion implant.26. The process as recited in claim 24, wherein step (b) comprisesdoping said dielectric layer with a series of ion implants.
 27. Theprocess as recited in claim 25, wherein step (b) comprises doping saiddielectric layer with a boron cluster.
 28. The process as recited inclaim 26 wherein step (b) comprises doping said dielectric layer with aboron implant followed by a hydrogen implant.
 29. The process as recitedin claim 24, wherein said semiconductor substrate is silicon.
 30. Theprocess as recited in claim 24, wherein said step (b) comprisesdepositing a layer of silicon dioxide.